Nvidia NVHBM Base Die With Samsung and TSMC

Seoul Economic Daily reported on 18 October 2026 that Nvidia is co-designing the base die of its proprietary high-bandwidth memory, NVHBM, with Samsung Electronics and TSMC, and that the base die is to use TSMC’s 3-nanometer logic process.

The English-language article is by Lee Seok-jin and cites unnamed industry sources. None of Nvidia, Samsung Electronics or TSMC is quoted confirming the arrangement. This is not presented here as a signed, publicly disclosed deal — only as what SED says its sources claim.

What SED says is being co-designed

SED writes: “Nvidia is co-designing the base die, a core component of its proprietary HBM called NVHBM, with Samsung Electronics and TSMC, industry sources said on the 18th.”

Per the same article, the base die sits at the bottom of the HBM stack and holds logic that shapes data-transfer behaviour. SED’s account of NVHBM’s design pitch:

It puts “the memory controller that previously sat on the GPU” onto the base die, freeing GPU area for more compute circuitry (SED’s description of Nvidia’s approach).
To make room, “the physical layer … was shrunk by 60% from standard HBM.”
“NVHBM can widen memory bandwidth by up to 30% and cut power consumption by 15% compared with standard HBM4E” — those percentages are figures in the SED article, not independently measured by TSN. The brief notes they align in direction with Nvidia’s own prior NVHBM bandwidth messaging; this post still attributes the 30%/15% pair to SED’s reporting.

For background on what custom HBM / NVHBM is meant to do, see TSN’s explainer What Is Custom HBM? Why Nvidia Wants to Move the Memory Controller Off the Chip.

Why TSMC 3nm, in SED’s telling

SED says Nvidia wants TSMC’s 3nm logic process for the base die because packing relocated GPU functions onto that die needs a fine process and a high yield. It then relays industry estimates (not company disclosures): “TSMC’s 3-nanometer yield at more than 90%, against roughly 60% for Samsung Foundry’s comparable 2-nanometer SF2 process.”

Those yield numbers are estimates attributed to “the industry” by SED. They are not confirmed here by TSMC or Samsung.

Samsung Foundry still preparing its own path

SED is careful not to say base-die production is locked exclusively at TSMC. While describing TSMC 3nm as Nvidia’s requested process, it reports that “Samsung Foundry is therefore validating NVHBM base die production on its 2-nanometer process,” quoting an unnamed industry official who also warned that TSMC 3nm capacity shared with HPC and smartphones “could hit a ceiling.”

Capacity colour in the same piece — TSMC adding 3nm lines at Fab 18 in Tainan, plus Arizona and Kumamoto timing — is SED summarising TSMC’s third-quarter earnings messaging, not a new TSMC announcement in this article. For TSMC’s own Q3 numbers and guidance, see TSN’s TSMC Q3 post; for an additional Tainan 3nm fab plan, see TSMC’s further 3nm fab reporting.

UBS demand projection (separate claim)

SED also cites UBS: HBM demand next year at “about 61.5 billion gigabits, a 91% increase,” with new shipments “only 54.6 billion gigabits,” implying “a supply shortfall of about 10%.” That is UBS’s projection as relayed by SED, not a market fact TSN has audited, and not a statement from Nvidia or the memory makers.

Related memory-capacity context on TSN includes Micron’s second Taiwan HBM plant.

What this post is not

A confirmed Nvidia–Samsung–TSMC joint press announcement
Proof that Samsung has abandoned its own base-die foundry plans
An independent verification of the 60% / 30% / 15% design claims or the 90% / 60% yield estimates
A forecast that NVHBM supply will clear any UBS-projected shortfall

Why it matters

If SED’s sources are right, Nvidia’s custom-HBM path is pulling a foundry rival pair — Samsung Electronics and TSMC — into the same base-die co-design, with logic on TSMC 3nm and Samsung still validating a 2nm alternative. That would matter for who captures custom-HBM base-die wafers as AI accelerators stay memory-bound. Until the companies speak, treat every operational detail as reported industry colour.

What’s still unknown

Whether Nvidia, Samsung Electronics or TSMC will confirm co-design or process node
Commercial split of NVHBM base-die wafer starts between TSMC and Samsung Foundry
Timing for volume production of any NVHBM stack using this base die
Primary text of the UBS note behind the 61.5 / 54.6 billion-gigabit figures

What this means

Seoul Economic Daily, citing unnamed sources, says Nvidia is co-designing the NVHBM base die with Samsung Electronics and TSMC for manufacture on TSMC 3nm, with Samsung Foundry also validating a 2nm path. Performance, yield and HBM-demand numbers in that story are SED’s attributed claims and estimates — not company confirmations and not TSN measurements.