Cadence Launches Maestro AI Models for Chip Design

Cadence Design Systems, which makes the software used to design chips, has launched its own family of AI models to run the agents it is building into its tools, and it will let customers keep them inside their own data centres.

The Maestro AI Model Portfolio, announced on 26 October, combines post-trained large language models, trained “decision models” and what Cadence calls self-improving agent skills, according to the company’s press release. The models power Cadence’s AI Super Agents, including AuraStack, ChipStack, InnoStack and ViraStack, which drive the company’s electronic design automation (EDA) and system design tools. The first models go to selected early-access customers in the fourth quarter of 2026.

Cadence says Maestro beats general-purpose models by up to 30%

Cadence says initial results show “up to 30% improvement in quality of results and up to 5X greater token efficiency versus a general-purpose foundation model.” Those are the company’s own figures. The release does not say which designs were tested, which general-purpose model was the baseline or how quality was scored, and the numbers have not been checked independently.

Cadence credits the gains to how the models are trained. Its tools and “deterministic solvers”, the conventional software that checks whether a design meets timing, power and other rules, score the models’ outputs against engineering targets, and those scores are fed back as reinforcement learning. Token efficiency comes partly from letting the agents call Cadence’s tools rather than asking the language model to work everything out, the company says.

NVIDIA helped build the portfolio. Maestro includes NVIDIA’s open-weight Nemotron models, and Cadence and NVIDIA are working on agent security through NVIDIA’s OpenShell reference architecture. “By grounding reinforcement learning in feedback from EDA tools and deterministic solvers, we can teach agents to make better design decisions based on how well their work meets engineering objectives and constraints,” said Tim Costa, vice president and general manager of industrial and computational engineering at NVIDIA. TSN reported earlier this month that NVIDIA had named Cadence among the chip companies using its CUDA-X libraries for design and manufacturing.

The release also quotes Japanese chip designer Socionext, which is putting Cadence’s InnoStack agent into its production physical design work. “We expect up to 5X overall productivity gains while maintaining design quality,” said Hisato Yoshida, Socionext’s chief operating officer. That is Socionext’s expectation for the agent, not a measured Maestro result.

Customers can run the models on their own hardware

Cadence says the full setup, agents, models and design tools, can run on Cadence’s cloud, on public clouds or “in a customer-controlled on-premises environment”. Customers can also post-train the Maestro models, including Nemotron, on their own designs and data. Paul Cunningham, a Cadence senior vice president, told The Next Platform that this customisation will be offered more as a managed service than something customers do alone.

Maestro is not the only model the agents use. Cadence’s product page says the Super Agents pick a mix of Maestro and outside “frontier and open-weight models” for each task.

Cadence is betting chipmakers want their designs kept at home

The choice puts Cadence on a different path from its largest rival. Synopsys said on 30 September that it would develop a model with OpenAI and share revenue with it, and that model, GPT-Synopsys, will run on OpenAI-hosted infrastructure, Reuters reported. Cadence is offering open-weight models that a chipmaker can run behind its own firewall.

That matters because a chip design is among the most closely guarded files a company owns. An unreleased processor layout is years of work and the basis of its next product. A model that can be trained on those designs without them leaving the building is an easier sell to that customer than a hosted one, whatever the benchmark says.

Cadence is not closing the door on the big labs. Cunningham told Reuters that “there are more (AI) model providers out there than there are (chip design software) vendors”, and said open- and closed-weight approaches are being “pursued equally”, with work with commercial labs “part of the Maestro vision”. He declined to give details.

The pitch also rests on tools rather than raw model strength. Cadence’s argument is that its solvers give it a source of verified feedback that a general model lacks, which is the same idea behind IBM Research’s experiment in which open AI agents sped up a quantum decoder chip design at a fraction of the cost of a proprietary model. Startups such as Cognichip are chasing the same market from outside the incumbents.

Whether the 30% holds outside Cadence’s own tests may become clearer once early-access customers start using Maestro in the fourth quarter. Until then, the more concrete difference between the two incumbents is where the model runs: on OpenAI’s servers for Synopsys, or on the customer’s own for Cadence.