Rambus said on 13 October 2026 that it has a new power management chip designed for LPDDR6 SOCAMM2, a type of low-power memory module for AI servers. The chip is “currently sampling to lead customers,” the company said, meaning a small number of early customers have test units [1]. Rambus calls the chip “industry-leading”; that is the company’s own description.
The memory it is built for is not on the market yet. In Rambus’s words, “LPDDR6 SOCAMM2, in development now, represents the next important evolution in LPDDR-based server memory technology” [1].
The terms, explained
- PMIC. A power management integrated circuit. It takes the electricity coming into a memory module and converts it into the exact, steady voltages the memory chips need. Rambus says its PMIC “efficiently steps down the system voltage supply to the voltage levels needed to power the LPDDR6 DRAM and all other active chips on the module” [1].
- LPDDR. Low-power double data rate memory, the kind of DRAM long used in phones and laptops because it uses less power. LPDDR6 is the next generation after today’s LPDDR5X.
- SOCAMM2. Rambus spells it out as “Small Outline Compression Attached Memory Modules” [1]. It is a compact, removable module that puts LPDDR memory into servers. Rambus says SOCAMM2 brings LPDDR’s power and performance benefits to “a compact, modular and serviceable server-memory architecture designed for demanding AI systems” [1]. Serviceable matters: low-power memory in phones is usually soldered down, while a module can be swapped.
- Tokens per watt. A way of measuring how much AI output, in tokens (pieces of text), a system produces for each unit of power. Rambus pitches the chip as helping to “scale tokens per watt for AI workloads” [1].
What the chip does
According to Rambus, the PMIC works alongside the Rambus SPD Hub, a chip that stores module information and handles monitoring. Together they provide “advanced power conversion, sequencing, telemetry and fault protection” for the module [1]. Rambus says it developed the PMIC “in technical cooperation with customers and ecosystem partners” but did not name them [1].
Rambus already sells what it calls “a complete LPDDR5X SOCAMM2 chipset” for the current generation of these modules [1]. The new PMIC extends that line to LPDDR6.
Rambus gave no efficiency figures, price or date for full production.
What Rambus and Micron said
Rami Sethi, who runs Rambus’s memory interface chips business, said: “Our new PMIC designed for LPDDR6 SOCAMM2 builds on our leadership in server-memory power management” [1].
Rambus’s release also quotes Praveen Vaidyanathan of Micron, which makes memory chips: “Micron has helped pioneer low-power memory for the data center and continues to work closely with ecosystem partners to advance industry standards such as SOCAMM2. We welcome Rambus’ continued investment in LPDDR6 power management solutions” [1].
What this means
- Power is the limit in AI data centres. Memory makers and chip suppliers are trying to squeeze more AI work out of each watt, and low-power phone-style memory is moving into servers.
- This is an early part. The chip is only sampling, and the LPDDR6 SOCAMM2 modules it serves are still in development.
- The supplier chain is lining up. Rambus makes the support chips on memory modules, not the memory itself, so its sampling suggests module makers are preparing for LPDDR6 SOCAMM2.
Sources
- Rambus, “Rambus Advances Power-Efficient AI Infrastructure with Industry-Leading PMIC Designed for LPDDR6 SOCAMM2”, San Jose, 13 October 2026. https://www.rambus.com/rambus-advances-power-efficient-ai-infrastructure-with-industry-leading-pmic-designed-for-lpddr6-socamm2/
